1. Field of the Invention
The present invention relates to a semiconductor memory device and more particularly, to a semiconductor memory device such as a static random-access memory (SRAM), in which each storage cell has a pair of complementary metal-oxide-semiconductor (CMOS) inverters providing a flip-flop circuit function.
2. Description of the Prior Art
A conventional SRAM has such a storage cell as shown in FIGS. 1A and 1B, FIGS. 2A and 2B, and FIG. 3. This cell is disclosed in 1991 IEDM Technical Digest, pp 481-484.
A circuit diagram of each storage cell of the conventional SRAM is shown in FIG. 3. There are first and second n-channel bulk MOS field-effect transistors (MOSFETs) 58 and 59 as driver transistors, first and second p-channel thin-film transistors (TFTs) 60 and 61 as load transistors, and third and fourth n-channel bulk MOS field-effect transistors 56 and 57 as access transistors.
Gates of the first driver MOS transistor 58 and the first load thin-film transistor 60 are coupled together, and drains or the first driver transistor 58 and the first load transistor 60 are coupled together. A source of the first driver transistor 58 is connected with the ground and a source of the first load transistor 60 is connected with a voltage source (supply voltage: V.sub.CC). Thus, the transistors 58 and 60 constitute a first CMOS inverter. The coupled gates of the transistors 58 and 60 form an input end of the first inverter, and their coupled drains form an output end thereof.
Similarly, gates of the second driver MOS transistor 59 and the second load thin-film transistor 61 are coupled together, and drains of the second driver transistor 59 and the second load transistor 61 are coupled together. A source of the second driver transistor 59 is connected with the ground and a source of the second load transistor 61 is connected with the voltage source. Thus, the transistors 59 and 61 constitute a second CMOS inverter. The coupled gates of the transistors 59 and 61 form an input end of the second inverter, and their coupled drains form an output end thereof.
The input end of the second inverter is connected with the output end of the first inverter and with a source of the first access transistor 56. A drain of the transistor 56 is connected with a first bit line 48-1 corresponding to this cell, and a gate thereof is connected with a word line W' corresponding to this cell.
The output end of the second inverter is connected with the input end of the first inverter and with a source of the second access transistor 57. A drain of the transistor 57 is connected with a second bit line 48-2 corresponding to this cell, and a gate thereof is connected with the word line W'.
The first and second inverters thus structured provide a flip-flop circuit function to store a data value therein.
The above storage cell is realized on a semiconductor substrate as follows:
FIGS. 1A and 1B show the plan view and the cross-sectional view of the storage cell, respectively.
As shown in FIG. 1B, a field insulator film 42 is selectively formed on a p-type silicon substrate 41 to form an isolation region thereon, providing active regions isolated by the isolation region on the substrate 41. A gate insulator film 44 is formed on the respective active regions at positions corresponding to gate electrodes of the MOS transistors 56, 57, 58 and 59.
FIG. 2A shows the layout of the bulk MOS transistors 56, 57, 58 and 59.
As shown in FIG. 2A, source and drain regions of the first driver MOS transistor 58 are made of n.sup.+ -type diffusion regions 46e and 46a formed in self-align to a gate electrode 45a in the substrate 41, respectively. The gate electrode 45a of the transistor 58 is formed on the gate insulator film 44 between the diffusion regions 46e and 46a.
Source and drain regions of the second driver MOS transistor 59 are made of n.sup.+ -type diffusion regions 46f and 46b formed in self-align to a gate electrode 45b in the substrate 41, respectively. The gate electrode 45b of the transistor 59 is formed on the gate insulator film 44 between the diffusion regions 46f and 46b.
Source and drain regions of the first access MOS transistor 56 are made of the n.sup.+ -type diffusion region 46a and an n.sup.+ -type diffusion region 46c formed in self-align to a gate electrode 45c in the substrate 41, respectively. The diffusion region 46a is sued for both of the transistors 56 and 58, in other words, the source region of the transistor 56 is connected with the drain region of the transistor 58. The diffusion region 46c as the drain region of the transistor 56 is connected with the first bit line 48-1 through a contact hole 47a. The hole 47a is formed to penetrate a first interlayer insulator film 67, a gate insulator film 50 for the thin-film transistors 60 and 61, and a second interlayer insulator film 68, as shown in FIG. 1B. The first bit line 48-1 is formed on the second interlayer insulator film 68.
The gate electrode 45c of the transistor 56 is formed on the gate insulator film 44 between the diffusion regions 46a and 46c. The gate electrode 45c is formed to be integrated with the word line W' corresponding to this cell.
Source and drain regions of the second access MOS transistor 57 are made of the n.sup.+ -type diffusion region 46b and an n.sup.+ -type diffusion region 46d formed in self-align to a gate electrode 45d in the substrate 41, respectively. The diffusion region 46b is used for both of the transistors 57 and 59, in other words, the source region of the transistor 57 is connected with the drain region of the transistor 59. The diffusion region 46d as the drain region of the transistor 57 is connected with the second bit line 48-2 through a contact hole 47b. The hole 47b also is formed to penetrate the first interlayer insulator film 67, the gate insulator film 50 for the thin-film transistors 60 and 61, and the second interlayer insulator film 68.
The gate electrode 45d of the transistor 57 is formed on the gate insulator film 44 between the diffusion regions 46b and 46d. The gate electrode 45d is formed to be integrated with the word line W'.
As shown in FIG. 1B, the first interlayer insulator film 67 is formed on the substrate 41 to cover the n.sup.+ -type diffusion regions 46a, 46b, 46c, 46d, 46e and 46f of the bulk MOS transistors 56, 57, 58 and 59, the gate electrode 45a, 45b, 45c and 45d thereof, and the field insulator film 42.
As shown in FIG. 1A, 1B and 2A, two contact holes 43a and 43b are formed in the gate insulator film 44, and two n.sup.+ -type diffusion regions 69 are formed in the substrate 41 at positions right below the contact holes 43a and 43b, respectively. The diffusion regions 69 are connected with the adjacent n.sup.+ -type diffusion regions 46a and 46b, respectively, so that the gate electrode 45b of the transistor 59 is connected with the diffusion region 46a through the contact hole 43a and the gate electrode 45a of the transistor 58 is connected with the diffusion region 46b through the contact hole 43b.
Next, the structures of the first and second thin-film transistors 60 and 61 are described referring to FIGS. 1B and 2B.
As shown in FIG. 1B, the first and second thin-film transistors 60 and 61 are formed on the first interlayer insulator film 67. Gate electrodes 49a and 49b for the transistors 60 and 61 are formed on the first interlayer insulator film 67. The gate electrode 49a of the transistor 60 is connected with the corresponding diffusion region 69 through a contact hole 54b of the first interlayer insulator film 67. Thus, the gate electrode 49a is electrically connected with the diffusion region 46b. The gate electrode 49b of the transistor 61 is connected with the corresponding diffusion region 69 through a contact hole 54a of the first interlayer insulator film 67. Thus, the gate electrode 49b is electrically connected with the diffusion region 46a.
The gate insulator film 50 for the transistors 60 and 61 is formed on the first interlayer insulator film 67 to cover the gate electrode 49a and 49b.
Source and drain regions 51a and 52a and a channel region 53a of the transistor 60 are formed by a polysilicon film. The polysilicon film is produced by the step of depositing an amorphous silicon film on the gate insulator film 50, the step of patterning the amorphous silicon film, and the step of annealing the amorphous film thus patterned so that this film is crystallized to be a polycrystalline silicon film with large-size grains. The source and drain regions 51a and 52a are doped with an impurity to be of a p.sup.+ -type. The channel region 53a is doped with no impurity.
The drain region 52a of the transistor 60 is connected with the gate electrode 49b of the transistor 61 through a contact hole 64a of the gate insulator film 50. The source region 51a thereof is connected with a power supply line 55.
Similarly, source and drain regions 51b and 52b and a channel region 53b of the transistor 61 are formed by a polysilicon film. The polysilicon film is produced by the same way as the case of the transistor 60. The source and drain regions 51b and 52b are doped with an impurity to be of a p.sup.+ -type. The channel region 53b is doped with no impurity.
The drain region 52b of the transistor 61 is connected with the gate electrode 49a of the transistor 60 through a contact hole 64b of the gate insulator film 50. The source region 51b thereof is connected with the power supply line 55.
The thin-film transistors 60 and 61 are covered with the second interlayer insulator film 68. The first and second bit lines 48-1 and 48-2 are formed on the film 68.
As described above, the storage cell of the conventional SRAM having the circuit of FIG. 3 is realized on the semiconductor substrate 41.
With the storage cell of the conventional SRAM, a data value is stored by using the electric potential difference at a node A', i.e., the diffusion region 46a and a node B', i.e., the diffusion region 46b. As a result, there is a problem that the content of the cell or the data value stored therein is destroyed if the supply voltage decreases drastically or if power is lost. This means that continuous power at a level higher than a specified one is essentially required for maintaining the stored data value.